This invention relates to a logic circuit test system for testing a logic circuit by supplying test patterns to the logic circuit and for comparing response outputs from the logic circuit with expected patterns, and more particularly to a logic circuit test system capable of changing the address sequence for generating the test patterns and the expected patterns.
In testing a logic circuit, test patterns and expected patters are simultaneously generated by a pattern generator provided in the logic circuit test system. The test patterns are supplied to a logic circuit under test and the resulting outputs from the logic circuit are compared by a comparator with the expected patterns to determine whether the logic circuit works correctly or not. Prior to supplying the test patterns to the logic circuit under test the logic circuit under test has to be set to an initial state, or to a reset state, for applying the test patterns beginning with the initial state. For initializing the logic circuit under test, the logic test system supplies, for instance, a reset signal to the logic circuit under test. The test patterns and expected patterns are data of plural bits, for respective pins of the logic circuit to be tested.
However, some logic circuits, for example, microprocessors or watch circuits and the like, do not have a special terminal such as a reset terminal for initializing their internal state. In the logic circuit of this kind, the internal state is incremented cyclically by a specific logic pattern inherent to the logic circuit (hereinafter referred to by increment pattern). By incrementing the internal state a predetermined number of times, for example 60 times, the internal state returns to the initial state. That is, by incrementing the internal state every 60 times as in the above example, the initial state of the logic circuit is repeatedly set. The number of times of applying the increment pattern to the logic circuit for repeating the same internal state is inherent to the logic circuit and is known from, for example, the technical description of the logic circuit under test. However, the internal state of the logic circuit under test at the time of beginning the application of the increment pattern is not known, since the internal state at that time depends on the previous operation of the logic circuit, or on the uncertainty which occurred when switching on the source power. Thus in the above example of repeating the same internal state when applying the increment pattern every 60 times, there is a possibility that the first initial state will occur on applying the increment pattern anywhere from 0 to 59 times, depending on the internal state just prior to the increment pattern.
For initializing and testing a logic circuit of this kind, a pattern generator disposed in the logic circuit test system repeatedly generates an increment pattern corresponding to the logic circuit that is to be tested for incrementing the internal state, and an expected pattern indicating the initial state of the logic circuit. The increment pattern is provided to the logic circuit under test, and the resulting output from the logic circuit under test is compared with the expected pattern by a comparator for detecting the initial state. When the output signal from the logic circuit and the expected pattern coincide with each other, a coincidence signal is generated by the comparator so that a logic circuit test is started by applying real test patterns for evaluating the logic circuit.
FIG. 1 shows a block diagram of a conventional logic circuit test system capable of testing a logic circuit of this kind. In FIG. 1, a program counter 101 is incremented by a clock signal 102. The program counter 101 provides the addresses 105 to a pattern generator 104. The other terminal of the program counter 101 is supplied with a coincidence signal 103 from a comparator 115. When the coincidence signal 103 is at low level, the program counter 101 repeatedly generates the address 0 of the pattern generator 104. On the other hand, when the coincidence signal 103 is at high level, the program counter 101 generates the address 105 incrementing by one step in synchronization with each clock signal 102 in the order of the addresses 1, 2, 3 . . . and provides the addresses to the pattern generator 104.
In the pattern generator 104, there are stored test patterns D.sub.n to D.sub.n for testing the logic circuit 109, expected patterns E.sub.0 to E.sub.n for comparison with the data from the logic circuit under test 109, and control data 1, 0, 0, 0 . . . for controlling the timing of the comparator 115 to selectively provide therefrom either a coincidence signal or a comparison signal. The test patterns, expected patterns and control data are selectively output as signals 107, 112 and 114, respectively. The test patterns from the pattern generator 104 are supplied to a formatter 106 in which the test patterns are shaped to predetermined logic waveforms such as return-to-zero (RZ), non-return-to zero (NRZ) signals and the like. The test patterns shaped and delivered by the formatter 106 are provided to a logic circuit 109 that is to be tested. When the test patterns are supplied, the logic circuit 109 provides the resulting output signal 110 to the comparator 115.
A delay circuit 111 adds delay time to the expected pattern 112 for adjusting the timing of comparing the output signal from the logic circuit 109 with the expected patterns, since both the formatter 106 and the logic circuit 109 have delay times for generating output signals. That is, the delay time of the delay circuit 111 is selected for providing the delayed expected pattern 117 to the comparator 115 at the same time that the output signal 110 from the logic circuit 109 is supplied to the comparator 115. Similarly, a delay circuit 113 is provided for delaying the control data 114 from the pattern generator 104 for adjusting the timing for selecting the outputs from the comparator 115.
The comparator 115 compares the output signal 110 from the logic circuit under test 109 with the delayed expected pattern 117, and allows a coincidence signal to be generated when the control data from the delay circuit 113 is at high level. When both signals coincide with each other and the control data is at high level, the coincidence signal 103 goes to high level. The coincidence signal 103 is used for detecting the initial state of the logic circuit, so that the test patterns are supplied to the logic circuit 109 after obtaining the initial state in the logic circuit 109. When the control data 118 is at low level, the comparator 115 provides a comparison signal at a terminal 119. That is, when the output signals from the logic circuit are not equal to the expected pattern 117, the comparator 115 generates a comparison signal indicating that the logic circuit under test does not work correctly and is thus to be eliminated. The timing for generating the coincidence signal or the comparison signal is determined by a strobe signal 120 supplied to the comparator 115. A delay time T.sub.d, between the clock signal 102 and the occurrence of the strobe pulse 120, is set to be equal to or greater than the sum of the delay times of the pattern generator 104, the formatter 106 and the logic circuit 109.
In the pattern generator 104 in FIG. 1, the expected pattern E.sub.0, which indicates the data equal to that of the output data of the logic circuit 109 when its internal state is set to the initial state, is stored in the address 0. The data D.sub.0 in the address 0 of the pattern generator 104 provides an increment pattern for sequentially incrementing the internal state of the logic circuit under test. The increment pattern D.sub.0 depends on the logic circuit that is to be tested, and is known beforehand from, for instance, the technical description of the logic circuit.
In the logic circuit test system of FIG. 1, at the start of the operation, the address 0 of the pattern generator 104 is repeatedly accessed by the program counter 101 for incrementing the internal state of the logic circuit 109. By comparing the output signal 110 of the logic circuit 109 with the expected pattern E.sub.0 indicating the initial state of the logic circuit 109 in each time slot, the logic circuit test system searches for the initial state of the logic circuit 109 to be tested. When the initial state is achieved, the comparator 115 provides the coincidence signal 103 to the program counter 101. After receiving the coincidence signal 103, the program counter 101 increments the address 105 sequentially in synchronism with the clock signal 102. Thus, the addresses 1,2,3 . . . of the pattern generator are sequentially accessed. In this way the logic circuit test system of FIG. 1 can test a logic circuit which does not have a terminal for being set to the initial state, such as a reset terminal, by supplying the test patterns sequentially to the logic circuit after the initial state is determined.
However, in this conventional logic circuit test system, if the time period of the clock signal 102 is smaller than the time required for generating the coincidence signal from the comparator 115 after the clock signal 102, that is, smaller than the delay time T.sub.d mentioned above, the internal state of the logic circuit under test is advanced to the next state by the increment pattern before being supplied with the actual test pattern following the increment pattern. Namely, in the logic circuit test system of FIG. 1, in the case that a delay time T.sub.d, which is determined by the strobe pulse 120 corresponding to the sum of the delay times of the pattern generator 104, the formatter 106 and the logic circuit 109, is greater than the time period of the clock signal 102, the internal state of the logic circuit 109 is incremented and becomes different from the initial state, as a result of the clock signal supplied during the delay time T.sub.d. Also, the number of steps of the difference from the initial state varies with change in the time period of the clock signal 102.
FIGS. 2-102 to 103 and 3-102 to -103 show timing charts for explaining the above problem. These are for the cases wherein the delay time T.sub.d is required for the coincidence signal 103 to be generated by the comparator 115, after the respective clock signal 102 is provided, and wherein the time period T.sub.p of the clock signal 102 is smaller than the delay time T.sub.d. It is assumed for the timing charts that the internal state of the logic circuit under test reaches the initial state during the second time slot, as a result of successively receiving the increment pattern D.sub.0. Namely, in the examples of the timing charts, the initial state is achieved by the increment pattern D.sub.0 corresponding to the second pulse 2 of the clock signal 102.
As illustrated in FIGS. 2-102 to -103, by the first pulse 1 of the clock signal 102, the increment pattern D.sub.0 is generated, and the logic circuit 109 is incremented by the increment pattern D.sub.0 so that the output is changed to a signal X after the delay time T.sub.d. As a result of the second pulse 2 of the clock signal 102, the output signal 110 of the logic circuit 109 eventually becomes E.sub.0, which indicates the initial state of the logic circuit 109. Since the output signal E.sub.0 and the expected pattern E.sub.0 are the same, the comparator 115 generates a coincidence signal 103 after the delay time T.sub.d. The program counter 101 generates the address 1 in response to the clock signal immediately following the coincidence signal 103, that is, in synchronism with the fifth pulse 5 of the clock signal 102. After that, the program counter 101 is incremented in the order of one step upon every occurrence of the clock signal 102, and thus the patterns D.sub.1, D.sub.2, D.sub.3 . . . , the expected patterns E.sub.1, E.sub.2 . . . and the control data 0, 0, 0 . . . are sequentially generated.
In the case of FIGS. 2-102 to 103, the output signal O.sub.1 in response to the test pattern D.sub.1 is derived after incrementing the internal state by two steps from the initial state. That is, the internal state of the logic circuit 109 is separated from the initial state E.sub.0 by the two steps A and B, as illustrated in FIG. 2-110. Since the test pattern D.sub.1 has to be supplied to the logic circuit 109 immediately after the initial state, the correct test result is not obtained from the output signal D.sub.1 which is three steps from the initial state. In FIG. 3-102 a longer period of the clock signal 102 than that of FIG. 2-102 is illustrated. The delay time T.sub.d illustrated in FIGS. 3-110 and -103 is identical to that of FIGS. 2-110 and -103, since the components are the same for both cases. As a result, in the case of FIG. 3 the internal state of the logic circuit 109 has advanced by only the one step A, when the test pattern D.sub.1 is supplied to the logic circuit 109.
Thus, in both the above cases, the internal state of the logic circuit under test differs from the initial state when the actual test patterns are provided after the increment pattern. Further, the number of steps by which the internal state differs from the initial state varies with the change of the period of the clock signal 102 as described above.
If the number of steps by which the internal state differs from the initial state is fixed and previously known, it is possible to test the logic circuit by supplying the test patterns successively after the initial state is provided in the logic circuit under test 109. For example, in the case of testing a logic circuit which repeats its internal states every 60 steps of the increment pattern, and for which the number of steps by which the internal state differs from the initial state is fixed for instance at 3, it is necessary to supply the increment pattern 57 times to the logic circuit 109, after the coincidence signal 103, to bring the logic circuit to the next initial state. Therefore, by supplying the test patterns D.sub.1 -D.sub.n, after repeating 57 times the supplying of the increment pattern D.sub.0, the test patterns can be sequentially supplied to the logic circuit successively beginning with the initial state of the logic circuit 109.
However, in the conventional logic circuit test system, the number of steps by which the internal state differs from the initial state varies with the period of the clock signal 102. In testing a logic circuit, it is important to evaluate the logic circuit by changing the repetition rate of the clock signal. Therefore, sufficient test results cannot be obtained for the logic circuit of the kind as described above with the prior art logic circuit test system.